Regviz

Freescale Semiconductor /MKV58F24 /PWM0 /SM2CTRL

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Interpret as SM2CTRL

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15 1211 87 43 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)DBLEN 0 (0)DBLX 0 (0)LDMOD 0 (000)PRSC0DT0 (0)FULL 0 (0)HALF 0 (0000)LDFQ

LDMOD=0, FULL=0, HALF=0, LDFQ=0000, DBLX=0, PRSC=000, DBLEN=0

Description

Control Register

Fields

DBLEN

Double Switching Enable

0 (0): Double switching disabled.

1 (1): Double switching enabled.
DBLX

PWMX Double Switching Enable

0 (0): PWMX double pulse disabled.

1 (1): PWMX double pulse enabled.
LDMOD

Load Mode Select

0 (0): Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL0[LDOK] is set.

1 (1): Buffered registers of this submodule are loaded and take effect immediately upon MCTRL0[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF].
PRSC

Prescaler

0 (000): PWM clock frequency = fclk

1 (001): PWM clock frequency = fclk/2

2 (010): PWM clock frequency = fclk/4

3 (011): PWM clock frequency = fclk/8

4 (100): PWM clock frequency = fclk/16

5 (101): PWM clock frequency = fclk/32

6 (110): PWM clock frequency = fclk/64

7 (111): PWM clock frequency = fclk/128
DT

Deadtime
FULL

Full Cycle Reload

0 (0): Full-cycle reloads disabled.

1 (1): Full-cycle reloads enabled.
HALF

Half Cycle Reload

0 (0): Half-cycle reloads disabled.

1 (1): Half-cycle reloads enabled.
LDFQ

Load Frequency

0 (0000): Every PWM opportunity

1 (0001): Every 2 PWM opportunities

2 (0010): Every 3 PWM opportunities

3 (0011): Every 4 PWM opportunities

4 (0100): Every 5 PWM opportunities

5 (0101): Every 6 PWM opportunities

6 (0110): Every 7 PWM opportunities

7 (0111): Every 8 PWM opportunities

8 (1000): Every 9 PWM opportunities

9 (1001): Every 10 PWM opportunities

10 (1010): Every 11 PWM opportunities

11 (1011): Every 12 PWM opportunities

12 (1100): Every 13 PWM opportunities

13 (1101): Every 14 PWM opportunities

14 (1110): Every 15 PWM opportunities

15 (1111): Every 16 PWM opportunities

Links

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data